Formal program transformations for VLSI circuit synthesis
Formal development programs and proofs
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 1992 IEEE/ACM international conference proceedings on Computer-aided design
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis and verification of asynchronous circuits from graphical specifications
Synthesis and verification of asynchronous circuits from graphical specifications
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Communicating sequential processes
Communications of the ACM
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Dynamic Hazards and Speed Independent Delay Model
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits
GLSVLSI '96 Proceedings of the 6th Great Lakes Symposium on VLSI
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We introduce a tabular method to perform the last two of the four phases of Martin's compilation process for asynchronous circuit design. The method is then demonstrated with three examples, illustrating that our systematic method is very straightforward, flexible, and convenient to apply, and, hence, it lends itself to automatic compilation.