Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Synthesizing Petri nets from state-based models
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of extended burst-mode circuits using generalized C-elements
EURO-DAC '96/EURO-VHDL '96 Proceedings of the conference on European design automation
Synthesis of speed-independent circuits from STG-unfolding segment
DAC '97 Proceedings of the 34th annual Design Automation Conference
Decomposition and technology mapping of speed-independent circuits using Boolean relations
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Asynchronous interface specification, analysis and synthesis
DAC '98 Proceedings of the 35th annual Design Automation Conference
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings
Formal Methods in System Design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Deriving Petri Nets from Finite Transition Systems
IEEE Transactions on Computers
Lazy transition systems: application to timing optimization of asynchronous circuits
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Detecting Exitory Stuck-At Faults in Semimodular Asynchronous Circuits
IEEE Transactions on Computers
Journal of VLSI Signal Processing Systems
Delay-insensitive interface specification and synthesis
DATE '00 Proceedings of the conference on Design, automation and test in Europe
An Improvement of McMillan's Unfolding Algorithm
Formal Methods in System Design
Designing Self-Timed Devices Using the Finite Automaton Model
IEEE Design & Test
High-Level Modeling and Design of Asynchronous Interface Logic
IEEE Design & Test
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of concurrency to system design
GALA (Globally Asynchronous - Locally Arbitrary) Design
Concurrency and Hardware Design, Advances in Petri Nets
Automatic Abstraction for Verification of Timed Circuits and Systems
CAV '01 Proceedings of the 13th International Conference on Computer Aided Verification
Synthesis of Reactive Systems: Application to Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Testing C-elements is not elementary
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Dynamic Logic in Four-Phase Micropipelines
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Dynamic Hazards and Speed Independent Delay Model
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Some Limitations to Speed-Independence in Asynchronous Circuits
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Counterflow Pipeline Based Dynamic Instruction Scheduling
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Behavioral Transformations to Increase Noise Immunity in Asynchronous Specifications
ASYNC '99 Proceedings of the 5th International Symposium on Advanced Research in Asynchronous Circuits and Systems
Low-Latency Contro Structures with Slack
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Design of Asynchronous Controllers with Delay Insensitive Interface
ASP-DAC '02 Proceedings of the 2002 Asia and South Pacific Design Automation Conference
STG Optimisation in the Direct Mapping of Asynchronous Circuits
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Hazard-free self-timed design: methodology and application
Integrated Computer-Aided Engineering
Integrated Computer-Aided Engineering
Synchronous elastic circuits with early evaluation and token counterflow
Proceedings of the 44th annual Design Automation Conference
A Region-Based Algorithm for Discovering Petri Nets from Event Logs
BPM '08 Proceedings of the 6th International Conference on Business Process Management
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hardware and Petri nets: application to asynchronous circuit design
ICATPN'00 Proceedings of the 21st international conference on Application and theory of petri nets
A low latency asynchronous arbitration circuit
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Microarchitectural Transformations Using Elasticity
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Constructive Boolean circuits and the exactness of timed ternary simulation
Formal Methods in System Design
Output-Determinacy and Asynchronous Circuit Synthesis
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
A structural encoding technique for the synthesis of asynchronous circuits
Fundamenta Informaticae - Application of Concurrency to System Design
Design and test of self-checking asynchronous control circuit
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
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