Symbolic Boolean manipulation with ordered binary-decision diagrams
ACM Computing Surveys (CSUR)
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Petri Net Analysis Using Boolean Manipulation
Proceedings of the 15th International Conference on Application and Theory of Petri Nets
Analysis of Petri Nets by Ordering Relations in Reduced Unfoldings
Formal Methods in System Design
Efficient encoding schemes for symbolic analysis of petri nets
Proceedings of the conference on Design, automation and test in Europe
Hierarchical gate-level verification of speed-independent circuits
ASYNC '95 Proceedings of the 2nd Working Conference on Asynchronous Design Methodologies
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
A Polynomial-Time Algorithm for Checking Consistency of Free-Choice Signal Transition Graphs
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
| Hi-index | 0.00 |
This paper defines conditions for a Signal Transition Graph to be implemented by an asynchronous circuit. A hierarchy of the implementability classes is presented. Our main concern is the implementability of the specification under the restricted input-output interface between the design and the environment, i.e., when no additional interface signals are allowed to be added to the design. We develop algorithms and present experimental results of using BDD-traversal for checking STG implementability. These results demonstrate efficiency of the symbolic approach and show a way of improving existing tools for STG-based asynchronous circuit design.