Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Branching processes of Petri nets
Acta Informatica
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
A unified signal transition graph model for asynchronous control circuit synthesis
Formal Methods in System Design
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Fundamenta Informaticae - Special issue on Petri nets
Symbolic Analysis of Bounded Petri Nets
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
An Improvement of McMillan's Unfolding Algorithm
Formal Methods in System Design
Decidability and Complexity of Petri Net Problems - An Introduction
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Canonical Prefixes of Petri Net Unfoldings
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Using Unfoldings to Avoid the State Explosion Problem in the Verification of Asynchronous Circuits
CAV '92 Proceedings of the Fourth International Workshop on Computer Aided Verification
Detecting State Coding Conflicts in STG Unfoldings Using SAT
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Partial order based approach to synthesis of speed-independent circuits.
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Detecting State Coding Conflicts in STGs Using Integer Programming
Proceedings of the conference on Design, automation and test in Europe
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Behaviour-preserving transition insertions in unfolding prefixes
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Combining decomposition and unfolding for STG synthesis
ICATPN'07 Proceedings of the 28th international conference on Applications and theory of Petri nets and other models of concurrency
Failures: their definition, modelling and analysis
ICTAC'07 Proceedings of the 4th international conference on Theoretical aspects of computing
A false history of true concurrency: from Petri to tools
SPIN'10 Proceedings of the 17th international SPIN conference on Model checking software
Efficient automatic resolution of encoding conflicts using STG unfoldings
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Generalised computation of behavioural profiles based on petri-net unfoldings
WS-FM'10 Proceedings of the 7th international conference on Web services and formal methods
Occurrence nets then and now: the path to structured occurrence nets
PETRI NETS'11 Proceedings of the 32nd international conference on Applications and theory of Petri Nets
On the construction of pullbacks for safe petri nets
ICATPN'06 Proceedings of the 27th international conference on Applications and Theory of Petri Nets and Other Models of Concurrency
Events, causality and symmetry
VoCS'08 Proceedings of the 2008 international conference on Visions of Computer Science: BCS International Academic Conference
Fundamenta Informaticae - Application of Concurrency to System Design, the Eighth Special Issue
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The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is deriving equations for logic gates implementing each output signal of the circuit. This is usually done using reachability graphs.In this paper, we avoid constructing the reachability graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. We propose an efficient algorithm for logic synthesis based on the Incremental Boolean Satisfiability (SAT) approach. Experimental results show that this technique leads not only to huge memory savings when compared with the methods based on reachability graphs, but also to significant speedups in many cases, without affecting the quality of the solution.