Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT

• Venue: ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
• Year: 2004

The behaviour of asynchronous circuits is often describedby Signal Transition Graphs (STGs), which arePetri nets whose transitions are interpreted as rising andfalling edges of signals. One of the crucial problems inthe synthesis of such circuits is deriving equations for logicgates implementing each output signal of the circuit. Thisis usually done using reachability graphs.In this paper, we avoid constructing the reachabilitygraph of an STG, which can lead to state space explosion,and instead use only the information about causality andstructural conflicts between the events involved in a finiteand complete prefix of its unfolding. We propose an efficientalgorithm for logic synthesis based on the IncrementalBoolean Satisfiability (SAT) approach. Experimental resultsshow that this technique leads not only to huge memorysavings when compared with the methods based on reachabilitygraphs, but also to significant speedups in many cases,without affecting the quality of the solution.