Trace theory for automatic hierarchical verification of speed-independent circuits
Trace theory for automatic hierarchical verification of speed-independent circuits
Arbiters: an exercise in specifying and decomposing asynchronously communicating components
Science of Computer Programming
On the models for asynchronous circuit behaviour with OR causality
Formal Methods in System Design
Communication and Concurrency
Input/Output Compatibility of Reactive Systems
FMCAD '02 Proceedings of the 4th International Conference on Formal Methods in Computer-Aided Design
Decomposition in Asynchronous Circuit Design
Concurrency and Hardware Design, Advances in Petri Nets
Logic Synthesis for Asynchronous Circuits Based on Petri Net Unfoldings and Incremental SAT
ACSD '04 Proceedings of the Fourth International Conference on Application of Concurrency to System Design
ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Strategies for Optimised STG Decomposition
ACSD '06 Proceedings of the Sixth International Conference on Application of Concurrency to System Design
Improved Decomposition of Signal Transition Graphs
Fundamenta Informaticae - The Fourth Special Issue on Applications of Concurrency to System Design (ACSD05)
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
Projection approaches to process mining using region-based techniques
Data Mining and Knowledge Discovery
Avoiding Irreducible CSC Conflicts by Internal Communication
Fundamenta Informaticae - Application of Concurrency to System Design
TCS'12 Proceedings of the 7th IFIP TC 1/WG 202 international conference on Theoretical Computer Science
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STGs (Signal Transition Graphs) give a formalism for the description of asynchronous circuits based on Petri nets. To overcome the state explosion problem one may encounter during circuit synthesis, a nondeterministic algorithm for decomposing STGs was suggested by Chu and improved by one of the present authors. Here we study how CSC-solving-which is essential for circuit synthesis-can be combined with decomposition. For this purpose, the correctness definition for decomposition is enhanced with internal signals and hierarchical decomposition is proven correct. Based on this, it is shown that speed-independent CSC-solving preserves correctness and can be combined with decomposition. Furthermore, we use our new correctness definition to give the first correctness proof for the decomposition method of Carmona and Cortadella. Finally, we compare three different implementation relations for STGs: one derived from our correctness definition; one defined by Dill based on trace structures; and one derived from I/O-compatibility defined by Carmona and Cortadella.