ILP Models for the Synthesis of Asynchronous Control Circuits
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
State encoding of large asynchronous controllers
Proceedings of the 43rd annual Design Automation Conference
Logic synthesis for asynchronous circuits based on STG unfoldings and incremental SAT
Fundamenta Informaticae - Special issue on application of concurrency to system design (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
On the Complexity of Consistency and Complete State Coding for Signal Transition Graphs
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Logic Synthesis for Asynchronous Circuits Based on STG Unfoldings and Incremental SAT
Fundamenta Informaticae - APPLICATION OF CONCURRENCY TO SYSTEM DESIGN (ACSD'04)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
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The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satis.es the Complete State Coding (CSC) requirement, e.g., by using model checking based on the state graph of an STG.In this paper, we avoid constructing the state graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. The algorithmis derived by adopting the Boolean Satisfiability (SAT) approach. This technique leads not only to huge memory savings when compared to methods based on state graphs, but also to significant speedups.