Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Branching processes of Petri nets
Acta Informatica
Symbolic model checking: an approach to the state explosion problem
Symbolic model checking: an approach to the state explosion problem
Concurrent hardware: the theory and practice of self-timed design
Concurrent hardware: the theory and practice of self-timed design
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
A technique of state space search based on unfolding
Formal Methods in System Design - Special issue on computer-aided verification (based on CAV'92 workshop)
A unified signal transition graph model for asynchronous control circuit synthesis
Formal Methods in System Design
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph
IEEE Transactions on Computers
Designing Control Logic for Counterflow Pipeline Processor Using Petri Nets
Formal Methods in System Design
Symbolic Analysis of Bounded Petri Nets
IEEE Transactions on Computers
Chaff: engineering an efficient SAT solver
Proceedings of the 38th annual Design Automation Conference
An Improvement of McMillan's Unfolding Algorithm
Formal Methods in System Design
Decidability and Complexity of Petri Net Problems - An Introduction
Lectures on Petri Nets I: Basic Models, Advances in Petri Nets, the volumes are based on the Advanced Course on Petri Nets
Canonical Prefixes of Petri Net Unfoldings
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
The Quest for Efficient Boolean Satisfiability Solvers
CAV '02 Proceedings of the 14th International Conference on Computer Aided Verification
Detecting State Coding Conflicts in STG Unfoldings Using SAT
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
CONFRES: Interactive Coding Conflict Resolver Based on Core Visualisation
ACSD '03 Proceedings of the Third International Conference on Application of Concurrency to System Design
Complete State Encoding Based on the Theory of Regions
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Partial order based approach to synthesis of speed-independent circuits.
ASYNC '97 Proceedings of the 3rd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Checking signal transition graph implementability by symbolic BDD traversal
EDTC '95 Proceedings of the 1995 European conference on Design and Test
Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings
CSD '98 Proceedings of the 1998 International Conference on Application of Concurrency to System Design
Detecting State Coding Conflicts in STGs Using Integer Programming
Proceedings of the conference on Design, automation and test in Europe
Visualization and Resolution of Coding Conflicts in Asynchronous Circuit Design
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Asynchronous circuit synthesis with Boolean satisfiability
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A Practical Approach to Verification of Mobile Systems Using Net Unfoldings
Fundamenta Informaticae - Petri Nets 2008
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'06)
Building Occurrence Nets from Reveals Relations
Fundamenta Informaticae
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The behaviour of asynchronous circuits is often described by Signal Transition Graphs (STGs), which are Petri nets whose transitions are interpreted as rising and falling edges of signals. One of the crucial problems in the synthesis of such circuits is that of identifying whether an STG satisfies the Complete State Coding (CSC) requirement (which states that semantically different reachable states must have different binary encodings), and, if necessary, modifying the STG (by, e.g. inserting new signals helping to trace the current state) to meet this requirement. This is usually done using reachability graphs. In this paper, we avoid constructing the reachability graph of an STG, which can lead to state space explosion, and instead use only the information about causality and structural conflicts between the events involved in a finite and complete prefix of its unfolding. We propose an efficient algorithm for detection of CSC conflicts based on the Boolean Satisfiability (SAT) approach. Following the basic formulation of the state encoding conflict relationship, we present some problem-specific optimization rules. Experimental results show that this technique leads not only to huge memory savings when compared to the CSC conflicts detection methods based on reachability graphs, but also to significant speedups in many cases.