Communications of the ACM
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Semi-modularity and testability of speed-independent circuits
Integration, the VLSI Journal - Special issue on high-level synthesis
Integration, the VLSI Journal
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Specification and analysis of self-timed circuits
Journal of VLSI Signal Processing Systems - Special issue: asynchronous circuit design for VLSI signal processing
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Computers and Intractability: A Guide to the Theory of NP-Completeness
Computers and Intractability: A Guide to the Theory of NP-Completeness
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
Synthesis of 3D Asynchronous State Machines
ICCD '92 Proceedings of the 1991 IEEE International Conference on Computer Design on VLSI in Computer & Processors
VLSI Programming of a Modulo-N Counter with Constant Response Time and Constant Power
Proceedings of the IFIP WG10.5 Working Conference on Asynchronous Design Methodologies
ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS
ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS
Direct synthesis of timed asynchronous circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
Detecting State Encoding Conflicts in STG Unfoldings Using SAT
Fundamenta Informaticae - Application of Concurrency to System Design (ACSD'03)
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To synthesize hazard-free asynchronous circuits from Signal Transition Graphs (STGs), we present a new Characteristic Graph (CG) to encapsulate all feasible solutions of the original STG in reduced size, which compares favorably with the state graph approach. Based on CG, we are able to explore the design space, as well as develop a necessary and sufficient condition for hazard-free realization on a predefined general circuit model, which has not yet been reported. The exact optimization for synthesis is shown to be NP hard. A heuristic method is thus proposed which results in efficient solutions while requiring very little CPU time.