On the models for designing VLSI asynchronous digital systems
Integration, the VLSI Journal
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
Synthesis of verifiably hazard-free asynchronous control circuits
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
VMEbus User's Handbook
Asynchronous Sequential Switching Circuit
Asynchronous Sequential Switching Circuit
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS
ANALYSIS OF PRODUCTION SCHEMATA BY PETRI NETS
A path-oriented approach for reducing hazards in asynchronous designs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Solving the state assignment problem for signal transition graphs
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Synthesis of concurrent system interface modules with automatic protocol conversion generation
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Basic gate implementation of speed-independent circuits
DAC '94 Proceedings of the 31st annual Design Automation Conference
A modular partitioning approach for asynchronous circuit synthesis
DAC '94 Proceedings of the 31st annual Design Automation Conference
Testing redundant asynchronous circuits by variable phase splitting
EURO-DAC '94 Proceedings of the conference on European design automation
A general state graph transformation framework for asynchronous synthesis
EURO-DAC '94 Proceedings of the conference on European design automation
Modeling and synthesis of timed asynchronous circuits
EURO-DAC '94 Proceedings of the conference on European design automation
Externally hazard-free implementations of asynchronous circuits
DAC '95 Proceedings of the 32nd annual ACM/IEEE Design Automation Conference
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
Efficient partial enumeration for timing analysis of asynchronous systems
DAC '96 Proceedings of the 33rd annual Design Automation Conference
Polynomial algorithms for the synthesis for hazard-free circuits from signal transition graphs
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Unifying synchronous/asynchronous state machine synthesis
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Synthesis of Hazard-Free Asynchronous Circuits Based on Characteristic Graph
IEEE Transactions on Computers
A unified signal transition graph model for asynchronous control circuit synthesis
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
A generalized state assignment theory for transformation on signal transition graphs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
On the verification of state-coding in STGs
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Verification of asynchronous interface circuits with bounded wire delays
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic synthesis of 3D asynchronous state machines
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Automatic gate-level synthesis of speed-independent circuits
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Exact two-level minimization of hazard-free logic with multiple-input changes
ICCAD '92 Proceedings of the 1992 IEEE/ACM international conference on Computer-aided design
Direct synthesis of timed asynchronous circuits
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
High-Speed Microprogrammable Asynchronous Controller Modules
IEEE Transactions on Computers
Hazards, Critical Races, and Metastability
IEEE Transactions on Computers
Automatic synthesis of gate-level timed circuits with choice
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Algorithms for the optimal state assignment of asynchronous state machines
ARVLSI '95 Proceedings of the 16th Conference on Advanced Research in VLSI (ARVLSI'95)
Automatic Synthesis of Speed-Independent Circuits from Signal Transition Graph Specifications
VLSID '96 Proceedings of the 9th International Conference on VLSI Design: VLSI in Mobile Communication
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