Communications of the ACM
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
Beauty is our business
Algorithms for synthesis of hazard-free asynchronous circuits
DAC '91 Proceedings of the 28th ACM/IEEE Design Automation Conference
Four State Asynchronous Architectures
IEEE Transactions on Computers
Implementing Sequential Machines as Self-Timed Circuits
IEEE Transactions on Computers
On the Delay-Sensitivity of Gate Networks
IEEE Transactions on Computers
Estimation of average switching activity in combinational and sequential circuits
DAC '92 Proceedings of the 29th ACM/IEEE Design Automation Conference
Performance analysis based on timing simulation
DAC '94 Proceedings of the 31st annual Design Automation Conference
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
Phased logic: a design methodology for delay-insensitive, synchronous circuitry
On the Interconnection of Asynchronous Control Structures
Journal of the ACM (JACM)
Algorithms for Synthesis and Testing of Asynchronous Circuits
Algorithms for Synthesis and Testing of Asynchronous Circuits
Recent Developments in the Design of Asynchronous Circuits
FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
A Coarse-Grain Phased Logic CPU
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
From Synchronous to Asynchronous: An Automatic Approach
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion
Proceedings of the 14th ACM Great Lakes symposium on VLSI
A Coarse-Grain Phased Logic CPU
IEEE Transactions on Computers
Design of a logic element for implementing an asynchronous FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Design automation of real-life asynchronous devices and systems
Foundations and Trends in Electronic Design Automation
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Transactions on Petri Nets and Other Models of Concurrency I
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
Automated Synchronous-to-Asynchronous Circuits Conversion: A Survey
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
An optimal design method for de-synchronous circuit based on control graph
APPT'07 Proceedings of the 7th international conference on Advanced parallel processing technologies
Asynchronous current mode serial communication
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Analysis of Static Data Flow Structures
Fundamenta Informaticae - Application of Concurrency to System Design, the Sixth Special Issue
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Phased logic is proposed as a solution to the increasing problem of timing complexity in digital design. It is a delay-insensitive design methodology that seeks to restore the separation between logical and physical design by eliminating the need to distribute low-skew clock signals and carefully balance propagation delays. However, unlike other methodologies that avoid clocks, phased logic supports the cyclic, deterministic behavior of the synchronous design paradigm. This permits the designer to rely chiefly on current experience and CAD tools to create phased logic systems. Marked graph theory is used as a framework for governing the interaction of phased logic gates that operate directly on Level-Encoded two-phase Dual-Rail (LEDR) signals. A synthesis algorithm is developed for converting clocked systems to phased logic systems and is applied to benchmark examples. Performance results indicate that phased logic tends to be tolerant of logic delay imbalances and has predictable worst-case timing behavior. Although phased logic requires additional circuitry, it has the potential to shorten the design cycle by reducing timing complexities.