Concurrent computations and VLSI circuits
Control Flow and Data Flow: concepts of distributed programming
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Switching and Finite Automata Theory: Computer Science Series
Switching and Finite Automata Theory: Computer Science Series
Introduction to VLSI Systems
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
Programming in VLSI: From Communicating Processes to Delay-Insensitive Circuits
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
The Design and Implementation of an On-Line Testable UART
Journal of Electronic Testing: Theory and Applications
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
An on-line testable UART implemented using IFIS
VTS '97 Proceedings of the 15th IEEE VLSI Test Symposium
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A self-timed finite state machine (FSM) is described. It is based on a formally proven, efficient implementation of self-timed combinational logic and a self-timed master-slave register. Temporal behavioral constraints are formalized, and the system is shown to abide by them. The synthesis method is algorithmic and serves as an automatic compiler of self-timed FSMs. The specification of the FSM is given by a state table, similar to that of synchronous machines. The circuit operates according to a sequence of events that replaces the role of the central clock in the synchronous FSM. The inputs and outputs of the circuit are double-rail (or ternary) and the circuit produces a completion signal. The method is compared with other approaches.