Fault diagnosis of digital circuits
Fault diagnosis of digital circuits
Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Implementing Sequential Machines as Self-Timed Circuits
IEEE Transactions on Computers
Diagnosis of leakage faults with IDDQ
Journal of Electronic Testing: Theory and Applications - Special issue on IDDQ testing of VLSI circuits
Introduction to VLSI Systems
Test Pattern Generation for Realistic Bridge Faults in CMOS ICs
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
Current vs. Logic Testing of Gate Oxide Short, Floating Gate and Bridging Failures in CMOS
Proceedings of the IEEE International Test Conference on Test: Faster, Better, Sooner
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This paper presents the design of a complex integrated circuitrealised through a novel on-line test methodology. The circuitand its exact conventional equivalent both have been realised inFPGA technology. As such it represents one of the most complexdesigns realised to date using on-line test approaches. Theapproach used—IFIS incorporates dual-rail coding of individualdata and a handshaking protocol, which substantially simplifiesthe detection of failure. Details of the IFIS methodology aregiven. The IFIS and conventional redesign of a commercial UARTare reported, focusing on methodological issues as well as sizeand speed. Output traces are shown for the IFIS UART on FPGAoperating under fault-free conditions and with deliberatefailures injected.