Concurrent computations and VLSI circuits
Control Flow and Data Flow: concepts of distributed programming
Implementing Sequential Machines as Self-Timed Circuits
IEEE Transactions on Computers
Logic Minimization Algorithms for VLSI Synthesis
Logic Minimization Algorithms for VLSI Synthesis
A Hardware Semantics Based on Temporal Intervals
Proceedings of the 10th Colloquium on Automata, Languages and Programming
Recent Developments in the Design of Asynchronous Circuits
FCT '89 Proceedings of the International Conference on Fundamentals of Computation Theory
Verification of Concurrent Programs: Temporal Proof Principles
Logic of Programs, Workshop
Limitations to Delay-Insensitivity in Asynchronous Circuits
Limitations to Delay-Insensitivity in Asynchronous Circuits
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
Implementing Sequential Machines as Self-Timed Circuits
IEEE Transactions on Computers
Partial scan delay fault testing of asynchronous circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
NULL Convention multiply and accumulate unit with conditional rounding, scaling, and saturation
Journal of Systems Architecture: the EUROMICRO Journal
Optimal Two-Level Delay - Insensitive Implementation of Logic Functions
PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation
Statechart methodology for the design, validation, and synthesis of large scale asynchronous systems
ASYNC '96 Proceedings of the 2nd International Symposium on Advanced Research in Asynchronous Circuits and Systems
Towards Totally Self-Checking Delay-Insensitive Systems
FTCS '95 Proceedings of the Twenty-Fifth International Symposium on Fault-Tolerant Computing
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Asynchronous gate-diffusion-input (GDI) circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and Analysis of Dual-Rail Circuits for Security Applications
IEEE Transactions on Computers
Speedup of NULL convention digital circuits using NULL cycle reduction
Journal of Systems Architecture: the EUROMICRO Journal
Design of a logic element for implementing an asynchronous FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Automated energy calculation and estimation for delay-insensitive digital circuits
Microelectronics Journal
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Registers for phase difference based logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware Implementation of Skeletonization Algorithm for Parallel Asynchronous Image Processing
Journal of Signal Processing Systems
Robust asynchronous implementation of Boolean functions on the basis of duality
ICC'10 Proceedings of the 14th WSEAS international conference on Circuits
A robust asynchronous early output full adder
WSEAS Transactions on Circuits and Systems
Formal Asynchronous Systems Modelling
Fundamenta Informaticae
Analog Integrated Circuits and Signal Processing
| Hi-index | 14.99 |
The authors propose a general synthesis method for efficiently implementing any family of Boolean functions over a set of variables, as a self-timed logic module. Interval temporal logic is used to express the constraints that are formulated for the self-timed logic module. A method is provided for proving the correct behavior of the designed circuit, by showing that it obeys all the functional constraints. The resulting circuit is compared with alternative proposed self-timed methodologies. This approach is shown to require less gates than other methods. The proposed method is appropriate for automatic synthesis of self-timed systems. A formal proof of correctness is provided.