Programming in VLSI: from communicating processes to delay-insensitive circuits
Developments in concurrency and communication
An Efficient Implementation of Boolean Functions as Self-Timed Circuits
IEEE Transactions on Computers
Integration, the VLSI Journal
Design of delay insensitive circuits using multi-ring structures
EURO-DAC '92 Proceedings of the conference on European design automation
Phased Logic: Supporting the Synchronous Design Paradigm with Delay-Insensitive Circuitry
IEEE Transactions on Computers
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
FPL '95 Proceedings of the 5th International Workshop on Field-Programmable Logic and Applications
High-level synthesis of asynchronous systems by data-driven decomposition
Proceedings of the 40th annual Design Automation Conference
ASAP '96 Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures, and Processors
Checking Delay-Insensitivity: 104 Gates and Beyond
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
A DESIGN METHODOLOGY FOR SELF-TIME SYSTEMS
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
Optimization of NULL convention self-timed circuits
Integration, the VLSI Journal
Logically Determined Design: Clockless System Design with NULL Convention Logic
Logically Determined Design: Clockless System Design with NULL Convention Logic
Design and characterization of NULL convention arithmetic logic units
Microelectronic Engineering
Design and characterization of convention self-timed multipliers
IEEE Design & Test
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
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Two versions of a reconfigurable logic element are developed for use in constructing a NULL convention logic (NCL) field-programmable gate array (FPGA): one with extra embedded registration capability, which requires additional area, and one without. Both versions can be configured as any of the 27 fundamental NCL gates, including resettable and inverting variations, and both can utilize embedded registration for gates with three or fewer inputs; however, only the version with the additional embedded registration capability can utilize embedded registration with four-input gates. These two approaches are compared with each other and with an existing approach, showing that both versions developed herein yield a more area efficient NCL circuit implementation, compared to the previous work. The two FPGA logic elements are simulated at the transistor level using the 1.8-V, 180-nm TSMC CMOS process.