VLSI array processors
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Self-timed rings and their application to division
Self-timed rings and their application to division
Signal processing at 250 MHz using high-performance FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Implementing Asynchronous Circuits on LUT Based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
The SFRA: a corner-turn FPGA architecture
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Highly pipelined asynchronous FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A Master-Slave Adaptive Load-Distribution Processor Model on PCA
IPDPS '05 Proceedings of the 19th IEEE International Parallel and Distributed Processing Symposium (IPDPS'05) - Workshop 3 - Volume 04
Dynamic loop pipelining in data-driven architectures
Proceedings of the 2nd conference on Computing frontiers
Asynchronous circuit design on reconfigurable devices
SBCCI '06 Proceedings of the 19th annual symposium on Integrated circuits and systems design
Tartan: evaluating spatial computation for whole program execution
Proceedings of the 12th international conference on Architectural support for programming languages and operating systems
Design of a logic element for implementing an asynchronous FPGA
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
An asynchronous fpga logic cell implementation
Proceedings of the 17th ACM Great Lakes symposium on VLSI
Design of an FPGA logic element for implementing asynchronous NULL convention logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
A Model of Computation for Bit-Level Concurrent Computing and Programming: APEC
IEICE - Transactions on Information and Systems
From synchronous to GALS: A new architecture for FPGAs
Microelectronics Journal
PRADA: a high-performance reconfigurable parallel architecture based on the dataflow model
International Journal of High Performance Systems Architecture
An implementation of an asychronous FPGA based on LEDR/four-phase-dual-rail hybrid architecture
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computing
International Journal of Reconfigurable Computing
A low-latency adaptive asynchronous interconnection network using bi-modal router nodes
NOCS '11 Proceedings of the Fifth ACM/IEEE International Symposium on Networks-on-Chip
Proceedings of the 17th IEEE/ACM international symposium on Low-power electronics and design
Synthesis and array processor realization of a 2-D IIR beam filter for wireless applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Asynchronous realization of algebraic integer-based 2D DCT using achronix speedster SPD60 FPGA
Journal of Control Science and Engineering - Special issue on Hardware Implementation of Digital Signal Processing Algorithms
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We discuss the design of a high-performance field programmable gate array (FPGA) architecture that efficiently prototypes asynchronous (clockless) logic. In this FPGA architecture, low-level application logic is described using asynchronous dataflow functions that obey a token-based compute model. We implement these dataflow functions using finely pipelined asynchronous circuits that achieve high computation rates. This asynchronous dataflow FPGA architecture maintains most of the performance benefits of a custom asynchronous design, while also providing postfabrication logic reconfigurability. We report results for two asynchronous dataflow FPGA designs that operate at up to 400 MHz in a typical TSMC 0.25\mu m CMOS process.