Implementing Asynchronous Circuits on LUT Based FPGAs

Authors:
Quoc Thai Ho;Jean-Baptiste Rigaud;Laurent Fesquet;Marc Renaudin;Robin Rolland
Affiliations:
-;-;-;-;-
Venue:
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Year:
2002

Citing 4
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Abstract

This paper describes a general methodology to rapidly prototype asynchronous circuits on LUT based FPGAs. The main objective is to offer designers the powerfulness of standard synchronous FPGAs to prototype their asynchronous circuits or mixed synchronous/asynchronous circuits. To avoid hazard in FPGAs, the appearance of hazard in configurable logic cells is analyzed. The developed technique is based on the use and the design of a Muller gate library. It is shown how the place and route tools automatically exploit this library. Finally, an asynchronous dual-rail adder is implemented automatically to demonstrate the potential of the methodology. Several FPGA families, like Xilinx X4000, Altera Flex, Xilinx Virtex and uptodate Altera Apex are targeted.