VLSI array processors
The design of an asynchronous microprocessor
Proceedings of the decennial Caltech conference on VLSI on Advanced research in VLSI
The limitations to delay-insensitivity in asynchronous circuits
AUSCRYPT '90 Proceedings of the sixth MIT conference on Advanced research in VLSI
Signal processing at 250 MHz using high-performance FPGA's
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
An FPGA for Implementing Asynchronous Circuits
IEEE Design & Test
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Implementing Asynchronous Circuits on LUT Based FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Slack Elasticity in Concurrent Computing
MPC '98 Proceedings of the Mathematics of Program Construction
PCA-1: A Fully Asynchronous, Self-Reconfigurable LSI
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
The Design of an Asynchronous MIPS R3000 Microprocessor
ARVLSI '97 Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97)
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
Automated synthesis for asynchronous FPGAs
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Owl: next generation system monitoring
Proceedings of the 2nd conference on Computing frontiers
Using GALS architecture to reduce the impact of long wire delay on FPGA performance
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Studying a GALS FPGA architecture using a parameterized automatic design flow
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
Design of a reconfigurable pulsed quad-cell for cellular-automata-based conformal computing
International Journal of Reconfigurable Computing
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We present the design of a high-performance, highly pipelined asynchronous FPGA. We describe a very fine-grain pipelined logic block and routing interconnect architecture, and show how asynchronous logic can efficiently take advantage of this large amount of pipelining. Our FPGA, which does not use a clock to sequence computations, automatically self-pipelines" its logic without the designer needing to be explicitly aware of all pipelining details. This property makes our FPGA ideal for throughput-intensive applications and we require minimal place and route support to achieve good performance. Benchmark circuits taken from both the asynchronous and clocked design communities yield throughputs in the neighborhood of 300--400 MHz in a TSMC 0.25m process and 500--700 MHz in a TSMC 0.18m process.