Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
VLSI array processors
The triptych FPGA architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic synthesis for large pass transistor circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Some experiments about wave pipelining on FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Signal processing at 250 MHz using high-performance FPGA's
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Wave steering in YADDs: a novel non-iterative synthesis and layout technique
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
A novel high throughput reconfigurable FPGA architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Wave-steering one-hot encoded FSMs
Proceedings of the 37th Annual Design Automation Conference
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Valid clock frequencies and their computation in wavepipelined circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Latency and latch count minimization in wave steered circuits
Proceedings of the 38th annual Design Automation Conference
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
PipeRoute: a pipelining-aware router for FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
PITIA: an FPGA for throughput-intensive applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Exploration of pipelined FPGA interconnect structures
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Highly pipelined asynchronous FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
An Asynchronous Dataflow FPGA Architecture
IEEE Transactions on Computers
Joint Application Mapping/Interconnect Synthesis Techniques for Embedded Chip-Scale Multiprocessors
IEEE Transactions on Parallel and Distributed Systems
A wire delay-tolerant reconfigurable unit for a clustered programmable-reconfigurable processor
Microprocessors & Microsystems
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS
WSEAS Transactions on Computers
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Wave-steering is a new design methodology that realizes high throughput circuits by embedding layout friendly synthesized structures in silicon. In the wave-steering design methodology, cir冒cuits inherently utilize latches. Inside the synthesized structures they are used for signal skewing, and on the interconnects to guar冒antee the correct arrival times at the inputs. Recently, we proposed a novel high-throughput FPGA architecture based on the wave-steering design principle to handle throughput-intensive applica冒tions. Previously our work was focussed mainly on the Logic Block (LB) design. In this paper we discuss a pipelined intercon冒nect scheme to support the strict timing requirements that is neces冒sitated by the wave-steered design style. We characterize designs that best fit the new architecture and show that as technology scales down towards deep submicron (DSM), this FPGA fabric shows an increasing throughput performance.