A novel high throughput reconfigurable FPGA architecture

Authors:
Amit Singh;Luca Macchiarulo;Arindam Mukherjee;Malgorzata Marek-Sadowska
Affiliations:
Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA;Department of Electrical and Computer Engineering, University of California, Santa Barbara, Santa Barbara, CA
Venue:
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Year:
2000

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Abstract

With increased logic density due to the shift towards Deep Submicron technologies (DSM), FPGAs have become a viable option for implementing large designs. However, most commercial FPGAs, due to their general purpose architectural nature, cannot handle designs which require very high throughput. In this paper, we propose a novel high throughput FPGA architecture which tries to combine the high-performance of Application Specific Integrated Circuits (ASICs) and the flexibility afforded by the reconfigurability of FPGAs. This architecture utilizes the concept of 'Wave-Steering' and works best for designs which are highly regular and have almost equal delays along all paths. It has enormous potential in Digital Signal and Image Processing applications since a good portion of these applications are regular in nature. Preliminary results for some commonly used DSP designs are encouraging and yield throughputs in the neighborhood of 770 MHz in 0.5&mgr; CMOS technology.