Field-programmable gate arrays
Field-programmable gate arrays
Placement and routing tools for the Triptych FPGA
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wormhole run-time reconfiguration
FPGA '97 Proceedings of the 1997 ACM fifth international symposium on Field-programmable gate arrays
FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
HSRA: high-speed, hierarchical synchronous reconfigurable array
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A reconfigurable arithmetic array for multimedia applications
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
A novel high throughput reconfigurable FPGA architecture
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Wave pipelining for application-specific networks-on-chips
CASES '02 Proceedings of the 2002 international conference on Compilers, architecture, and synthesis for embedded systems
An FPGA architecture with enhanced datapath functionality
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
RaPiD - Reconfigurable Pipelined Datapath
FPL '96 Proceedings of the 6th International Workshop on Field-Programmable Logic, Smart Applications, New Paradigms and Compilers
A Negative-Overhead, Self-Timed Pipeline
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Garp: a MIPS processor with a reconfigurable coprocessor
FCCM '97 Proceedings of the 5th IEEE Symposium on FPGA-Based Custom Computing Machines
A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications
FCCM '98 Proceedings of the IEEE Symposium on FPGAs for Custom Computing Machines
FCCM '00 Proceedings of the 2000 IEEE Symposium on Field-Programmable Custom Computing Machines
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
FPGA clock network architecture: flexibility vs. area and power
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A Jitter Attenuating Timing Chain
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
The Lee Path Connection Algorithm
IEEE Transactions on Computers
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
A Network of Time-Division Multiplexed Wiring for FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Implementation of Wave-Pipelined Interconnects in FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Estimating reliability and throughput of source-synchronous wave-pipelined interconnect
NOCS '09 Proceedings of the 2009 3rd ACM/IEEE International Symposium on Networks-on-Chip
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
The effect of LUT and cluster size on deep-submicron FPGA performance and density
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2002 international symposium on low-power electronics and design (ISLPED)
The effect of multi-bit correlation on the design of field-programmable gate array routing resources
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Effect of the prefabricated routing track distribution on FPGA area-efficiency
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelining: a tutorial and research survey
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this work, we investigate the effect of serialization on the implementation area of datapath circuits on FPGAs. With ever-increasing logic capacity, FPGAs are being increasingly used to implement large datapath circuits. Since datapath circuits are designed to process multiple-bit wide data, FPGA routing resources, which typically consist of a significant amount of FPGA area, are routinely being used to transport multiple-bit wide signals. Consequently, it is important to design efficient routing architectures for transporting multiple-bit wide signals on FPGAs. Serialization, where several bits of a signal are first time-multiplexed and then transported over a single wire, has been effectively used to increase the I/O bandwidth of FPGAs. Recent work has proposed to use serialization to increase the area efficiency of FPGA routing resources for transporting multiple-bit wide signals. Most of the work, however, has focused on circuit-level design issues. Little work has been done on the overall effect of serialization on the area efficiency of FPGAs. In this work, we investigate the overall effect of serialization on the area efficiency of FPGAs. We propose a detailed FPGA routing architecture, which contains a set of serialization routing resources, and its associated routing tool. Using the architecture and the tool, we measure the effect of serialization on active area and track count. We found that, for benchmarks that contain four-bit wide datapath circuits, serialization can achieve a maximum active area reduction of 6.4% and a routing track reduction of 29%.