Efficient self-timing with level-encoded 2-phase dual-rail (LEDR)
Proceedings of the 1991 University of California/Santa Cruz conference on Advanced research in VLSI
Interconnect pipelining in a throughput-intensive FPGA architecture
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
The case for registered routing switches in field programmable gate arrays
FPGA '01 Proceedings of the 2001 ACM/SIGDA ninth international symposium on Field programmable gate arrays
Interconnect enhancements for a high-speed PLD architecture
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
Pausible Clocking: A First Step Toward Heterogeneous Systems
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
ASYNC '01 Proceedings of the 7th International Symposium on Asynchronous Circuits and Systems
A Negative-Overhead, Self-Timed Pipeline
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
Jitter in Deep Sub-Micron Interconnect
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A Jitter Attenuating Timing Chain
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
A Survey and Taxonomy of GALS Design Styles
IEEE Design & Test
Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays
Journal of Signal Processing Systems
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
Implementation of Wave-Pipelined Interconnects in FPGAs
NOCS '08 Proceedings of the Second ACM/IEEE International Symposium on Networks-on-Chip
Routability of network topologies in FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CMOS VLSI Design: A Circuits and Systems Perspective
CMOS VLSI Design: A Circuits and Systems Perspective
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Wave-pipelined intra-chip signaling for on-FPGA communications
Integration, the VLSI Journal
Effect of serialized routing resources on the implementation area of datapath circuits on FPGAS
WSEAS Transactions on Computers
Quantifying the cost and benefit of latency insensitive communication on FPGAs
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
Integration, the VLSI Journal
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FPGA user clocks are slow enough that only a fraction of the interconnect's bandwidth is actually used. There may be an opportunity to use throughput-oriented interconnect to decrease routing congestion and wire area using on-chip serial signaling, especially for datapath designs which operate on words instead of bits. To do so, these links must operate reliably at very high bit rates. We compare wave pipelining and surfing source-synchronous schemes in the presence of power supply and crosstalk noise. In particular, supply noise is a critical modeling challenge; better models are needed for FPGA power grids. Our results show that wave pipelining can operate at rates as high as 5Gbps for short links, but it is very sensitive to noise in longer links and must run much slower to be reliable. In contrast, surfing achieves a stable operating bit rate of 3Gbps and is relatively insensitive to noise.