VPR: A new packing, placement and routing tool for FPGA research
FPL '97 Proceedings of the 7th International Workshop on Field-Programmable Logic and Applications
High-Speed QDI Asynchronous Pipelines
ASYNC '02 Proceedings of the 8th International Symposium on Asynchronus Circuits and Systems
A High-Speed Clockless Serial Link Transceiver
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
ASYNC '05 Proceedings of the 11th IEEE International Symposium on Asynchronous Circuits and Systems
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A 3Gb/s/wire Global On-Chip Bus with Near Velocity-of-Light Latency
VLSID '06 Proceedings of the 19th International Conference on VLSI Design held jointly with 5th International Conference on Embedded Systems Design
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
A survey of research and practices of Network-on-chip
ACM Computing Surveys (CSUR)
Optimization techniques for FPGA-based wave-pipelined DSP blocks
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Congestion estimation and localization in fpgas:: a visual tool for interconnect prediction
Proceedings of the 2007 international workshop on System level interconnect prediction
High Rate Wave-pipelined Asynchronous On-chip Bit-serial Data Link
ASYNC '07 Proceedings of the 13th IEEE International Symposium on Asynchronous Circuits and Systems
Using metro-on-chip in physical design flow for congestion and routability improvement
Microelectronics Journal
Global interconnections in FPGAs: modeling and performance analysis
Proceedings of the 2008 international workshop on System level interconnect prediction
RF interconnects for communications on-chip
Proceedings of the 2008 international symposium on Physical design
Improving FPGA routability using network coding
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
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Asynchronous serial transceivers have been recently used for data serializing in large on-chip systems to alleviate the routing congestion and improve the routability. FPGAs have considerable potential for using the asynchronous serial transmission but they have serious challenges to use this technology. In this paper, we present a new FPGA architecture corresponding with a new routing algorithm to use the asynchronous data serializing technique in modern FPGAs. Experimental results show that allocated routing tracks and routing congestion can be reduced considerably (18.81% and 48.73%, respectively) by using the asynchronous data serializing without any performance degradation in cost of reasonable overhead in area and power consumption. The resulting improvements will increase for larger and more complex FPGAs.