The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Thermal via placement in 3D ICs
Proceedings of the 2005 international symposium on Physical design
Implementing Caches in a 3D Technology for High Performance Processors
ICCD '05 Proceedings of the 2005 International Conference on Computer Design
A thermal-driven floorplanning algorithm for 3D ICs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Fast Asynchronous Shift Register for Bit-Serial Communication
ASYNC '06 Proceedings of the 12th IEEE International Symposium on Asynchronous Circuits and Systems
Temperature-aware routing in 3D ICs
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Serial-link bus: a low-power on-chip bus architecture
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
3D floorplanning with thermal vias
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Design and Management of 3D Chip Multiprocessors Using Network-in-Memory
Proceedings of the 33rd annual international symposium on Computer Architecture
Efficient thermal-oriented 3D floorplanning and thermal via planning for two-stacked-die integration
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Three-dimensional integrated circuits
IBM Journal of Research and Development - Advanced silicon technology
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Performance Evaluation for Three-Dimensional Networks-On-Chip
ISVLSI '07 Proceedings of the IEEE Computer Society Annual Symposium on VLSI
Interconnects in the third dimension: design challenges for 3D ICs
Proceedings of the 44th annual Design Automation Conference
HPCA '07 Proceedings of the 2007 IEEE 13th International Symposium on High Performance Computer Architecture
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Parallel vs. serial on-chip communication
Proceedings of the 2008 international workshop on System level interconnect prediction
MIRA: A Multi-layered On-Chip Interconnect Router Architecture
ISCA '08 Proceedings of the 35th Annual International Symposium on Computer Architecture
Serialized asynchronous links for NoC
Proceedings of the conference on Design, automation and test in Europe
Three-dimensional Integrated Circuit Design
Three-dimensional Integrated Circuit Design
Supporting vertical links for 3D networks-on-chip: toward an automated design and analysis flow
Proceedings of the 2nd international conference on Nano-Networks
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A low-overhead fault tolerance scheme for TSV-based 3D network on chip links
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
A multilayer nanophotonic interconnection network for on-chip many-core communications
Proceedings of the 47th Design Automation Conference
OPAL: a multi-layer hybrid photonic NoC for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Vertical interconnects squeezing in symmetric 3D mesh network-on-chip
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Cluster-based topologies for 3D stacked architectures
Proceedings of the 8th ACM International Conference on Computing Frontiers
Power and area optimization of 3D networks-on-chip using smart and efficient vertical channels
PATMOS'11 Proceedings of the 21st international conference on Integrated circuit and system design: power and timing modeling, optimization, and simulation
HPC-Mesh: A Homogeneous Parallel Concentrated Mesh for Fault-Tolerance and Energy Savings
Proceedings of the 2011 ACM/IEEE Seventh Symposium on Architectures for Networking and Communications Systems
Adaptive inter-layer message routing in 3D networks-on-chip
Microprocessors & Microsystems
Evaluation of using inductive/capacitive-coupling vertical interconnects in 3D network-on-chip
Proceedings of the International Conference on Computer-Aided Design
CSL: Configurable Fault Tolerant Serial Links for Inter-die Communication in 3D Systems
Journal of Electronic Testing: Theory and Applications
Three-dimensional Integrated Circuits: Design, EDA, and Architecture
Foundations and Trends in Electronic Design Automation
Distributed sensor data processing for many-cores
Proceedings of the great lakes symposium on VLSI
Developing a power-efficient and low-cost 3D NoC using smart GALS-based vertical channels
Journal of Computer and System Sciences
Cluster-based topologies for 3D Networks-on-Chip using advanced inter-layer bus architecture
Journal of Computer and System Sciences
Deflection routing in 3D network-on-chip with limited vertical bandwidth
ACM Transactions on Design Automation of Electronic Systems (TODAES) - Special Section on Networks on Chip: Architecture, Tools, and Methodologies
Integration, the VLSI Journal
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
Graceful deadlock-free fault-tolerant routing algorithm for 3D Network-on-Chip architectures
Journal of Parallel and Distributed Computing
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Three-dimensional integrated circuits (3D ICs) offer a promising solution to overcome the on-chip communication bottleneck and improve performance over traditional two-dimensional (2D) ICs. Long interconnects can be replaced by much shorter vertical through silicon via (TSV) interconnects in 3D ICs. This enables faster and more power efficient inter-core communication across multiple silicon layers. However, 3D IC technology also faces challenges due to higher power densities and routing congestion due to TSV pads distributed on each layer. In this paper, serialization of vertical TSV interconnects in 3D ICs is proposed as one way to address these challenges. Such serialization reduces the interconnect TSV footprint on each layer. This can lead to a better thermal TSV distribution resulting in lower peak temperatures, as well as more efficient core layout across multiple layers due to the reduced congestion. Experiments with several 3D multi-core benchmarks indicate clear benefits of serialization. For instance, a 4:1 serialization of TSV interconnects can save more than 70% of TSV area footprint at a negligible performance and power overhead at the 65nm technology node.