Quo vadis, BTSoC (billion transistor SoC)?
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Memory-aware NoC exploration and design
Proceedings of the conference on Design, automation and test in Europe
System-level PVT variation-aware power exploration of on-chip communication architectures
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 Asia and South Pacific Design Automation Conference
Exploring hybrid photonic networks-on-chip foremerging chip multiprocessors
CODES+ISSS '09 Proceedings of the 7th IEEE/ACM international conference on Hardware/software codesign and system synthesis
Exploring serial vertical interconnects for 3D ICs
Proceedings of the 46th Annual Design Automation Conference
Configurable SID-based multi-core simulators for embedded system education
WESE '09 Proceedings of the 2009 Workshop on Embedded Systems Education
Profiling-based hardware/software co-exploration for the design of video coding architectures
IEEE Transactions on Circuits and Systems for Video Technology
MPSoC bus architecture optimization under performance constraints for multiple applications
ISCIT'09 Proceedings of the 9th international conference on Communications and information technologies
OE+IOE: a novel turn model based fault tolerant routing scheme for networks-on-chip
CODES/ISSS '10 Proceedings of the eighth IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
New heuristic algorithms for energy aware application mapping and routing on mesh-based NoCs
Journal of Systems Architecture: the EUROMICRO Journal
Topology synthesis for low power cascaded crossbar switches
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Hierarchical circuit-switched NoC for multicore video processing
Microprocessors & Microsystems
Evaluating carbon nanotube global interconnects for chip multiprocessor applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
OPAL: a multi-layer hybrid photonic NoC for 3D ICs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Stochastic communication for application-specific Networks-on-Chip
The Journal of Supercomputing
Power Modeling and Characterization of Computing Devices: A Survey
Foundations and Trends in Electronic Design Automation
Modular performance simulations of clouds
Proceedings of the Winter Simulation Conference
Automatic design of low-power encoders using reversible circuit synthesis
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
Journal of Electronic Testing: Theory and Applications
Microprocessors & Microsystems
Virtualized and fault-tolerant inter-layer-links for 3D-ICs
Microprocessors & Microsystems
On the design space exploration through the Hellfire Framework
Journal of Systems Architecture: the EUROMICRO Journal
METEOR: Hybrid photonic ring-mesh network-on-chip for multicore architectures
ACM Transactions on Embedded Computing Systems (TECS) - Special Issue on Design Challenges for Many-Core Processors, Special Section on ESTIMedia'13 and Regular Papers
High-speed dynamic TDMA arbiter for inter-layer communications in 3-D network-on-chip
Journal of High Speed Networks
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Over the past decade, system-on-chip (SoC) designs have evolved to address the ever increasing complexity of applications, fueled by the era of digital convergence. Improvements in process technology have effectively shrunk board-level components so they can be integrated on a single chip. New on-chip communication architectures have been designed to support all inter-component communication in a SoC design. These communication architecture fabrics have a critical impact on the power consumption, performance, cost and design cycle time of modern SoC designs. As application complexity strains the communication backbone of SoC designs, academic and industrial R&D efforts and dollars are increasingly focused on communication architecture design. This book is a comprehensive reference on concepts, research and trends in on-chip communication architecture design. It will provide readers with a comprehensive survey, not available elsewhere, of all current standards for on-chip communication architectures. KEY FEATURES* A definitive guide to on-chip communication architectures, explaining key concepts, surveying research efforts and predicting future trends* Detailed analysis of all popular standards for on-chip communication architectures* Comprehensive survey of all research on communication architectures, covering a wide range of topics relevant to this area, spanning the past several years, and up to date with the most current research efforts* Future trends that with have a significant impact on research and design of communication architectures over the next several years