The SPLASH-2 programs: characterization and methodological considerations
ISCA '95 Proceedings of the 22nd annual international symposium on Computer architecture
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Optimum wire sizing of RLC interconnect with repeaters
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Extending the transaction level modeling approach for fast communication architecture exploration
Proceedings of the 41st annual Design Automation Conference
Performance analysis of carbon nanotube interconnects for VLSI applications
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
System-level power-performance trade-offs in bus matrix communication architecture synthesis
CODES+ISSS '06 Proceedings of the 4th international conference on Hardware/software codesign and system synthesis
Proceedings of the 2007 international workshop on System level interconnect prediction
Investigating the Design, Performance, and Reliability of Multi-Walled Carbon Nanotube Interconnect
ISQED '08 Proceedings of the 9th international symposium on Quality Electronic Design
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Fixed-outline floorplanning: enabling hierarchical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Luttinger liquid theory as a model of the gigahertz electrical properties of carbon nanotubes
IEEE Transactions on Nanotechnology
Modeling Crosstalk Effects in CNT Bus Architectures
IEEE Transactions on Nanotechnology
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Journal of Computational Electronics
Delay uncertainty in single- and multi-wall carbon nanotube interconnects
VDAT'12 Proceedings of the 16th international conference on Progress in VLSI Design and Test
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In ultra-deep submicrometer (UDSM) technologies, the current paradigm of using copper (Cu) interconnects for on-chip global communication is rapidly becoming a serious performance bottleneck. In this paper, we perform a system level evaluation of Carbon Nanotube (CNT) interconnect alternatives that may replace conventional Cu interconnects. Our analysis explores the impact of using CNT global interconnects on the performance and energy consumption of several multi-core chip multiprocessor (CMP) applications. Results from our analysis indicate that with improvements in fabrication technology, CNT-based global interconnects can significantly outperform Cu-based global interconnects.