Inductance 101: modeling and extraction

Authors:
Michael W. Beattie;Lawrence T. Pileggi
Affiliations:
Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania, 15213;Carnegie Mellon University, Department of Electrical and Computer Engineering, 5000 Forbes Avenue, Pittsburgh, Pennsylvania, 15213
Venue:
Proceedings of the 38th annual Design Automation Conference
Year:
2001

Citing 2
Cited 16

A wide frequency range surface integral formulation for 3-D RLC extraction

ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Inductance 101: analysis and design issues

Proceedings of the 38th annual Design Automation Conference

Inductance Modeling for On-Chip Interconnects

Analog Integrated Circuits and Signal Processing
INDUCTWISE: inductance-wise interconnect simulator and extractor

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
SCORE: SPICE COmpatible Reluctance Extraction

Proceedings of the conference on Design, automation and test in Europe - Volume 2
Mutual inductance extraction and the dipole approximation

Proceedings of the 2004 international symposium on Physical design
CHIME: coupled hierarchical inductance model evaluation

Proceedings of the 41st annual Design Automation Conference
Frequency-dependent reluctance extraction

Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Reduced Delay Uncertainty in High Performance Clock Distribution Networks

DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Design and Measurement of an Inductance-Oscillator for Analyzing On-Chip Inductance Impact on Wire Delay

Analog Integrated Circuits and Signal Processing
An efficient algorithm for 3-D reluctance extraction considering high frequency effect

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits

ACM Journal on Emerging Technologies in Computing Systems (JETC)
On-Chip Communication Architectures: System on Chip Interconnect

On-Chip Communication Architectures: System on Chip Interconnect
Modeling of the performance of carbon nanotube bundle, cu/low-k and optical on-chip global interconnects

Proceedings of the 2007 international workshop on System level interconnect prediction
Accurate loop self inductance bound for efficient inductance screening

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Evaluating carbon nanotube global interconnects for chip multiprocessor applications

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Inductance modelling of SWCNT bundle interconnects using partial element equivalent circuit method

Journal of Computational Electronics
Power Equations and Capacity Performance of Magnetic Induction Communication Systems

Wireless Personal Communications: An International Journal

Quantified Score

Hi-index	0.00

Visualization

Abstract

Modeling magnetic interactions for on-chip interconnect has become an issue of great interest for inte-grated circuit design in recent years. This tutorial paper de-scribes the basic concepts of magnetic interaction, loop and partial inductance, along with some of the high frequency ef-fects such as skin and proximity effect.