Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
On-chip inductance issues in multiconductor systems
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance modeling and analysis
Proceedings of the 37th Annual Design Automation Conference
Inductance 101: modeling and extraction
Proceedings of the 38th annual Design Automation Conference
Min/max on-chip inductance models and delay metrics
Proceedings of the 38th annual Design Automation Conference
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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A newly devised inductance-oscillator (iOSC) has been developed which evaluates inductance impact on on-chip wire delay. iOSC is a ring oscillator which is comprised of a set of wires each with different loop inductance and accurate on-chip counter. The equivalent distance to the nearest ground grid, which serves as the current return path, is varied to control wire inductance.A test chip using 0.13-驴m node process is fabricated to demonstrate concept of the iOSC. Four wire structures are implemented as imperfect coplanar waveguide, imitating clock lines or high-frequency global signal lines. The structure with largest inductance variation measured 99 ps delay difference while newly proposing twisted ground structure which has small inductance variation measured 6 ps both for 3-mm wires. This experiment also provides designers with a guideline for ground density from inductance standpoint. iOSC confirms that the inductance impact on delay has to be adequately analyzed and controlled to estimate a timing in high-speed LSI designs.