Layout techniques for minimizing on-chip interconnect self inductance

Authors:
Yehia Massoud;Steve Majors;Tareq Bustami;Jacob White
Affiliations:
Mass. Institute of Tech., Dept. of Elect. Eng., Cambridge, MA;Rockwell Semiconductor Systems, Austin, TX and Motorola Inc., Somerset Design Center, Austin, TX;Motorola Inc., Somerset Design Center, Austin, TX;Mass. Institute of Tech., Dept of Elect. Eng., Cambridge, MA
Venue:
DAC '98 Proceedings of the 35th annual Design Automation Conference
Year:
1998

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Abstract

Because magnetic effects have a much longer spatial range than electrostatic effects, an interconnect line with large inductance will be sensitive to distant variations in interconnect topology. This long range sensitivity makes it difficult to balance delays in nets like clock trees, so for such nets inductance must be minimized. In this paper we use two- and three-dimensional electromagnetic field solvers to compare dedicated ground planes to a less area-consuming approach, interdigitating the signal line with ground lines. The surprising conclusion is that with very little area penalty, interdigitated ground lines are more effective at minimizing self-inductance than ground planes.