Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Active shields: a new approach to shielding global wires
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Research directions for coevolution of rules and routers
Proceedings of the 2003 international symposium on Physical design
Efficient on-chip crosstalk avoidance CODEC design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In this paper we apply the concept of active shielding to inductive global interconnections. Active shields, which are shield wires that are switched at the same time as the signal wire, were initially developed to speed global signal propagation in RC dominated lines by ensuring in-phase switching of adjacent nets. This work further investigates this concept by examining RLC wiring. We find a distinct line width crossover point at which in-phase switching of neighbors no longer offers benefits and where the increased inductive behavior introduces substantial ringing. We propose the use of out-of-phase active shielding for such wide inductive lines. This technique is shown to significantly reduce ringing behavior (up to 4.5X) and offer better slopes (up to 40% reduction) and signal propagation delays, all of which are shown in the context of a clock net optimization.