Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
Dealing with inductance in high-speed chip design
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Resistive and inductive skin effect in rectangular conductors
IBM Journal of Research and Development
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Until now, the miniaturization by scaling law has developed the technology of VLSI circuits. With this miniaturization much faster speed and much better performance circuits have been obtained. This miniaturization is expected to continue and the clock speed will become much faster than now, which means that we have to encounter a problem that is caused by inductance. In these background there are a lot of papers in extraxting inductance. At the same time calculating inductance is considered very tiresome task because it needs a lot of computational cost of that. In this paper we introduce new ideas and new methods to reduce computational cost of calculating inductance. We have developed a frequency dependent inductance calculation simulator for cost reduction of calculating inductance and found that the results of the simulator had a good agreement with those of the conventional methods. With this simulator we also show some effects of inductance in circuit behavior.