Layout techniques for minimizing on-chip interconnect self inductance
DAC '98 Proceedings of the 35th annual Design Automation Conference
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Interconnect parasitic extraction in the digital IC design methodology
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Clocktree RLC extraction with efficient inductance modeling
DATE '00 Proceedings of the conference on Design, automation and test in Europe
On the impact of on-chip inductance on signal nets under the influence of power grid noise
Proceedings of the conference on Design, automation and test in Europe
Multi-GHz interconnect effects in microprocessors
Proceedings of the 2001 international symposium on Physical design
Technical visualizations in VLSI design: visualization
Proceedings of the 38th annual Design Automation Conference
Built-in self-test for signal integrity
Proceedings of the 38th annual Design Automation Conference
Proceedings of the 38th annual Design Automation Conference
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Signal Integrity: Fault Modeling and Testing in High-Speed SoCs
Journal of Electronic Testing: Theory and Applications
Testing Interconnects for Noise and Skew in Gigahertz SoCs
ITC '01 Proceedings of the 2001 IEEE International Test Conference
Impact of On-Chip Inductance When Transitioning from Al to Cu Based Technology
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Computational Cost Reduction in Extracting Inductance
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A metric for analyzing effective on-chip inductive coupling
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Analysis of high-performance clock networks with RLC and transmission line effects
Proceedings of the 12th ACM/IEEE international workshop on System level interconnect prediction
On the impact of on-chip inductance on signal nets under the influence of power grid noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Myth busters: microprocessor clocking is from Mars, ASICs clocking is from Venus
Proceedings of the International Conference on Computer-Aided Design
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