Clocktree RLC extraction with efficient inductance modeling

Authors:
Norman Chang;Shen Lin;Lei He;O. Sam Nakagawa;Weize Xie
Affiliations:
Hewlett-Packard Laboratories, Palo Alto, CA;Hewlett-Packard Laboratories, Palo Alto, CA;ECE Dept., University of Wisconsin, Madison, WI;Hewlett-Packard Laboratories, Palo Alto, CA;Hewlett-Packard Laboratories, Palo Alto, CA
Venue:
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Year:
2000

Numerical recipes in C (2nd ed.): the art of scientific computing

Numerical recipes in C (2nd ed.): the art of scientific computing
High speed CMOS design styles

High speed CMOS design styles
Dealing with inductance in high-speed chip design

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
On-chip inductance issues in multiconductor systems

Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Interconnect Analysis and Synthesis

Interconnect Analysis and Synthesis

An efficient model for frequency-dependent on-chip inductance

GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Analysis of on-chip inductance effects using a novel performance optimization methodology for distributed RLC interconnects

Proceedings of the 38th annual Design Automation Conference
On the efficacy of simplified 2D on-chip inductance models

Proceedings of the 39th annual Design Automation Conference
Effective On-chip Inductance Modeling for Multiple Signal Lines and Application on Repeater Insertion

ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Quick On-Chip Self- and Mutual-Inductance Screen

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Modeling of coplanar waveguide for buffered clock tree

Proceedings of the 2004 Asia and South Pacific Design Automation Conference

Hi-index	0.00