Mixed-swing quadrail for low power dual-rail domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
GLSVLSI '00 Proceedings of the 10th Great Lakes symposium on VLSI
Clocktree RLC extraction with efficient inductance modeling
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Hybrid structured clock network construction
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
A technique for improving dual-output domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Efficient Self-Timed Interfaces for Crossing Clock Domains
ASYNC '03 Proceedings of the 9th International Symposium on Asynchronous Circuits and Systems
Interconnect-Dominated VLSI Design
ARVLSI '99 Proceedings of the 20th Anniversary Conference on Advanced Research in VLSI
Current-Mode Threshold Logic Gates
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
DFT for Delay Fault Testing of High-Performance Digital Circuits
IEEE Design & Test
Reducing pipeline energy demands with local DVS and dynamic retiming
Proceedings of the 2004 international symposium on Low power electronics and design
Low-power circuits and technology for wireless digital systems
IBM Journal of Research and Development
Mixed-clock issue queue design for energy aware, high-performance cores
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
Toward stochastic design for digital circuits: statistical static timing analysis
Proceedings of the 2004 Asia and South Pacific Design Automation Conference
A low-power reduced swing global clocking methodology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Critical evaluation of SOI design guidelines
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Increasing the energy efficiency of pipelined circuits via slack redistribution
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Fault Modeling and Simulation of Power Supply Voltage Transients in Digital Systems on a Chip
Journal of Electronic Testing: Theory and Applications
Self-reset logic for fast arithmetic applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Silicon virtual prototyping: the new cockpit for nanometer chip design
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Design of a 1.7-GHz low-power delay-fault-testable 32-b ALU in 180-nm CMOS technology
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Mixed Full Adder topologies for high-performance low-power arithmetic circuits
Microelectronics Journal
ReCycle:: pipeline adaptation to tolerate process variation
Proceedings of the 34th annual international symposium on Computer architecture
Testable designs of multiple precharged domino circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding the Effect of Intradie Random Process Variations in Nanometer Domino Logic
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Impact of supply voltage variations on full adder delay: analysis and comparison
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Built-in sensor for signal integrity faults in digital interconnect signals
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Understanding the effect of process variations on the delay of static and domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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