A technique for improving dual-output domino logic

Authors:
Sumant Ramprasad;Ibrahim N. Hajj;Farid N. Najm
Affiliations:
Mindspeed Technologies Inc., Newport Beach, CA;American University of Beirut, Beirut, Lebanon and the Coordinated Science Laboratory, University of Illinois at Urbana-Champaign, Urbana, IL;Department of Electrical and Computer Engineering, University of Toronto, Toronto, ON M5S 3G4, Canada
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2002

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Abstract

We present a technique, termed clock-generating (CG) domino, for improving dual-output domino logic that reduces area, clock load and power without increasing the delay. A delayed clock, generated from certain dual-output gates, is used to convert other dual-output gates to single output. Simulation results with ISCAS 85 benchmark circuits indicate an average reduction in area, clock load, and power of 17%, 20%, and 24%, respectively, over dual-output domino and a 48% power reduction for the largest circuit.