Inverter minimization in multi-level logic networks
ICCAD '93 Proceedings of the 1993 IEEE/ACM international conference on Computer-aided design
Graph Algorithms
Domino logic synthesis using complex static gates
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Automated phase assignment for the synthesis of low power domino circuits
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
An optimization technique for dual-output domino logic
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Timing-driven partitioning for two-phase domino and mixed static/domino implementations
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Implication graph based domino logic synthesis
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Technology mapping algorithms for domino logic
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A technique for improving dual-output domino logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Design and synthesis of dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on system-level interconnect prediction (SLIP)
Synthesis of Dual-VT Dynamic CMOS Circuits
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Opportunities and challenges in application-tuned circuits and architectures based on nanodevices
Proceedings of the 1st conference on Computing frontiers
Characterization of logic circuit techniques for high leakage CMOS technologies
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Post-layout logic optimization of domino circuits
Proceedings of the 41st annual Design Automation Conference
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Integer linear programming-based synthesis of skewed logic circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Post-layout logic duplication for synthesis of domino circuits with complex gates
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Crosstalk-aware domino logic synthesis
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Postlayout optimization for synthesis of Domino circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Characterization of logic circuit techniques and optimization for high-leakage CMOS technologies
Integration, the VLSI Journal - Special issue: ACM great lakes symposium on VLSI
Technology mapping for SOI domino logic incorporating solutions for the parasitic bipolar effect
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Domino logic is one of the most popular dynamic circuit configurations for implementing high-performance logic designs. Since domino logic is inherently noninverting, it presents a fundamental constraint of implementing logic functions without any intermediate inversions. Removal of intermediate inverters requires logic duplication for generating both the negative and positive signal phases, which results in significant area overhead. This area overhead can be substantially reduced by selecting an optimal output phase assignment, which results in a minimum logic duplication penalty for obtaining inverter-free logic. In this paper, we present this previously unaddressed problem of output phase assignment for minimum area duplication in dynamic logic synthesis. We give both optimal and heuristic algorithms for minimizing logic duplication.