Timing-driven partitioning for two-phase domino and mixed static/domino implementations

Authors:
Min Zhao;Sachin S. Sapatnekar
Affiliations:
ECE Department, University of Minnesota, Minneapolis, MN;ECE Department, University of Minnesota, Minneapolis, MN
Venue:
ICCAD '99 Proceedings of the 1999 IEEE/ACM international conference on Computer-aided design
Year:
1999

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Abstract

Domino logic is a high-performance circuit configuration that is usually embedded in static logic environment and tightly coupled with the clocking scheme. In this paper, the timing-driven partitioning algorithms that partition a logic network between (1) static and domino implementations, and (2) the phases of a two-phase clock, are provided. In addition, an efficient static mapping algorithm is described.