Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Design and optimization of dual-threshold circuits for low-voltage low-power applications
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low power synthesis of dual threshold voltage CMOS VLSI circuits
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Technology and design challenges for low power and high performance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Clock-Delayed Domino for Adder and Combinational Logic Desig
ICCD '96 Proceedings of the 1996 International Conference on Computer Design, VLSI in Computers and Processors
CMOS Digital Integrated Circuits Analysis & Design
CMOS Digital Integrated Circuits Analysis & Design
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
| Hi-index | 0.00 |
This paper presents S2 L, which exhibits low power; high-speed with use of positive feedback circuits and dual Vt. Topology-dependent dual Vt approach suppresses leakage current while boosting the performance in VDSM technology. S2 L consumes less dynamic and static power compared to Monotonic Static (MS) CMOS. We present simulation results of NAND-NOR gate chains and 32-b adders to demonstrate the effectiveness of the S2 L compared to other techniques. Design automation for the proposed circuit architecture can be achieves d easily due to cascading flexibility.