Optimal orientations of cells in slicing floorplan designs
Information and Control
Corolla based circuit partitioning and resynthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Technology mapping for domino logic
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design and Synthesis of Monotonic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
High-Performance, Low-Power Skewed Static Logic in Very Deep-Submicron (VDSM) Technology
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Synthesis of Selectively Clocked Skewed Logic Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Integer linear programming-based synthesis of skewed logic circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Low power synthesis of dynamic logic circuits using fine-grained clock gating
Proceedings of the conference on Design, automation and test in Europe: Proceedings
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Skewed logic circuits belong to a noise-tolerant high-performance static circuit family. Skewed logic circuits can achieve performance comparable to that of Domino logic circuits but with much lower power consumption. Two factors contribute to the reduction in power. First, by exploiting the static nature of skewed logic circuits, we can alleviate the cost of logic duplication which is typically required to overcome the logic reconvergence problem in both Domino logic and skewed logic circuits. Second, a selective clocking scheme can be applied to a skewed logic circuit to reduce the clock load and hence, clock power. In this article, we propose a two-step synthesis scheme of skewed logic circuits. In the first step, an integer linear programming-based approach is presented to overcome the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. In the second step, a dynamic programming-based heuristic is applied to achieve an optimal selective clocking scheme. Experimental results show that the average power saving of skewed logic circuits over Domino logic circuits is 41.1&percent;.