Corolla based circuit partitioning and resynthesis
DAC '90 Proceedings of the 27th ACM/IEEE Design Automation Conference
Logic optimization by output phase assignment in dynamic logic synthesis
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Design and Synthesis of Monotonic Circuits
ICCD '99 Proceedings of the 1999 IEEE International Conference on Computer Design
Skewed CMOS: Noise-Immune High-Performance Low-Power Static Circuit Family
ICCD '00 Proceedings of the 2000 IEEE International Conference on Computer Design: VLSI in Computers & Processors
Synthesis of Selectively Clocked Skewed Logic Circuits
ISQED '02 Proceedings of the 3rd International Symposium on Quality Electronic Design
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
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We present an integer linear programming-based approach for solving the logic reconvergence problem in skewed logic circuits with minimal logic duplication cost. A simplification technique is applied to reduce the complexity of the ILP problem greatly so that the run time is more affordable. Experimental results show that an average of 18% of original gates are duplicated in skewed logic circuits, whereas 65% in Domino logic circuits are duplicated. The average power saving over Domino logic circuits is 40.9%.