Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications

Authors:
Naran Sirisantana;Aiqun Cao;Shawn Davidson;Cheng Kok Koh;Kaushik Roy
Affiliations:
School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN;School of Electrical and Computer Engineering, Purdue University, West Lafayette, IN
Venue:
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Year:
2001

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