Monotonic static CMOS and dual-VT technology
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Dynamic noise analysis in precharge-evaluate circuits
Proceedings of the 37th Annual Design Automation Conference
A 13.3ns double-precision floating-point ALU and multiplier
ICCD '95 Proceedings of the 1995 International Conference on Computer Design: VLSI in Computers and Processors
Selectively clocked skewed logic (SCSL): low-power logic style for high-performance applications
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
O2 ABA: a novel high-performance predictable circuit architecture for the deep submicron era
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Comparison of noise tolerant precharge (NTP) to conventional feedback keepers for dynamic logic
Proceedings of the 13th ACM Great Lakes symposium on VLSI
Selectively Clocked CMOS Logic Style for Low-Power Noise-Immune Operations in Scaled Technologies
DATE '03 Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Enhancing Yield at the End of the Technology Roadmap
IEEE Design & Test
Synthesis of skewed logic circuits
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Integer linear programming-based synthesis of skewed logic circuits
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
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In this paper, we present a noise-immune high-performance static circuit family suitable for low-voltage operation called skewed logic. Skewed logic circuits, in comparison with Domino logic, have better scalability, and they are more suitable for low voltage applications because of better noise margin. Skewed logic has been compared with Domino logic in terms of delay, power, and dynamic noise immunity. A design methodology for skewed CMOS pipelined circuits has been developed. Comparisons between skewed and Domino circuits on a 0.25 µm 700 MHz 16 x 16 bits pipelined multiplier show superior properties of skewed circuits over Domino in terms of clock power dissipation and peak current consumption.