Dynamic noise analysis in precharge-evaluate circuits

Authors:
Dinesh Somasekhar;Seung Hoon Choi;Kaushik Roy;Yibin Ye;Vivek De
Affiliations:
Dept. of ECE, Purdue University, W.Lafayette, IN;Dept. of ECE, Purdue University, W.Lafayette, IN;Dept. of ECE, Purdue University, W.Lafayette, IN;Intel Corp., Hillsboro, OR;Intel Corp., Hillsboro, OR
Venue:
Proceedings of the 37th Annual Design Automation Conference
Year:
2000

Citing 2
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Abstract

A dynamic noise model is developed and applied to analyze the noise immunity of precharge-evaluate circuits. Considering that the primary source of noise-injection in the circuit is cross-talk, a simple metric represented as voltage-time product can be used to quantify the dynamic noise-margin. This is verified by HSPICE simulation on DOMINO gates. A tool is also developed to obtain static and dynamic noise-margins at various points in the circuit. Dynamic noise-margins are translated into maximum allowable coupling capacitances between the pairs of nets for precharge-evaluate logic circuits. An accurate estimate of dynamic noise-margin and coupling coefficient bounds will allow improvement of the circuits in terms of robustness.