Practical methods of optimization; (2nd ed.)
Practical methods of optimization; (2nd ed.)
A view of unconstrained optimization
Optimization
Efficient small-signal circuit analysis and sensitivity computations with the PVL algorithm
ICCAD '94 Proceedings of the 1994 IEEE/ACM international conference on Computer-aided design
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
CUTE: constrained and unconstrained testing environment
ACM Transactions on Mathematical Software (TOMS)
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Optimization of custom MOS circuits by transistor sizing
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Performance optimization of VLSI interconnect layout
Integration, the VLSI Journal
Power supply noise analysis methodology for deep-submicron VLSI chip design
DAC '97 Proceedings of the 34th annual Design Automation Conference
Circuit optimization via adjoint Lagrangians
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimization Software Guide
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Statistical Modeling for Computer-Aided Design of MOS VLSI Circuits
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Sensitivity and Optimization
Numerical Methods for Unconstrained Optimization and Nonlinear Equations (Classics in Applied Mathematics, 16)
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
Optimal design of macrocells for low power and high speed
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
JiffyTune: circuit optimization using time-domain sensitivities
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Dynamic noise analysis in precharge-evaluate circuits
Proceedings of the 37th Annual Design Automation Conference
A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Analog Integrated Circuits and Signal Processing
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The relentless push for high performance in custom digital circuits has led to renewed emphasis on circuit optimization or tuning. The parameters of the optimization are typically transistor and interconnect sizes. The design metrics are not just delay, transition times, power and area, but also signal integrity and manufacturability. This tutorial paper discusses some of the recently proposed methods of circuit optimization, with an emphasis on practical application and methodology impact. Circuit optimization techniques fall into three broad categories. The first is dynamic tuning, based on time-domain simulation of the underlying circuit, typically combined with adjoint sensitivity computation. These methods are accurate but require the specification of input signals, and are best applied to small data-flow circuits and "cross-sections" of larger circuits. Efficient sensitivity computation renders feasible the tuning of circuits with a few thousand transistors. Second, static tuners employ static timing analysis to evaluate the performance of the circuit. All paths through the logic are simultaneously tuned, and no input vectors are required. Large control macros are best tuned by these methods. However, in the context of deep submicron custom design, the inaccuracy of the delay models employed by these methods often limits their utility. Aggressive dynamic or static tuning can push a circuit into a precipitous corner of the manufacturing process space, which is a problem addressed by the third class of circuit optimization tools, statistical tuners. Statistical techniques are used to enhance manufacturability or maximize yield. In addition to surveying the above techniques, topics such as the use of state-of-the-art nonlinear optimization methods and special considerations for interconnect sizing, clock tree optimization and noise-aware tuning will be briefly considered.