Direct methods for sparse matrices
Direct methods for sparse matrices
SIAM Journal on Numerical Analysis
Transistor size optimization in the tailor layout system
DAC '89 Proceedings of the 26th ACM/IEEE Design Automation Conference
A new modified Cholesky factorization
SIAM Journal on Scientific and Statistical Computing
SIAM Journal on Numerical Analysis
Simultaneous driver and wire sizing for performance and power optimization
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low-power design
CUTE: constrained and unconstrained testing environment
ACM Transactions on Mathematical Software (TOMS)
A sequential quadratic programming approach to concurrent gate and wire sizing
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Power vs. delay in gate sizing: conflicting objectives?
ICCAD '95 Proceedings of the 1995 IEEE/ACM international conference on Computer-aided design
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Lancelot: A FORTRAN Package for Large-Scale Nonlinear Optimization (Release A)
Electronic Circuit & System Simulation Methods (SRE)
Electronic Circuit & System Simulation Methods (SRE)
The future of custom cell generation in physical synthesis
DAC '97 Proceedings of the 34th annual Design Automation Conference
Optimization techniques for high-performance digital circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Circuit optimization via adjoint Lagrangians
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Migration: a new technique to improve synthesized designs through incremental customization
DAC '98 Proceedings of the 35th annual Design Automation Conference
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Overview of continuous optimization advances and applications to circuit tuning
Proceedings of the 2001 international symposium on Physical design
ISVLSI '05 Proceedings of the IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design
Effective analytical delay model for transistor sizing
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimizing performances of switched current memory cells through a heuristic
Analog Integrated Circuits and Signal Processing
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
A novel Alienor-based heuristic for the optimal design of analog circuits
Microelectronics Journal
The opportunity cost of low power design: a case study in circuit tuning
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
A novel heuristic for multi-objective optimization of analog circuit performances
Analog Integrated Circuits and Signal Processing
Analog circuit design optimization through the particle swarm optimization technique
Analog Integrated Circuits and Signal Processing
Power optimization methodology for the IBM POWER7 microprocessor
IBM Journal of Research and Development
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Optimization of a circuit by transistor sizing is often a slow, tedious and iterative manual process which relies on designer intuition. Circuit simulation is carried out in the inner loop of this tuning procedure. Automating the transistor sizing process is an important step towards being able to rapidly design high-performance, custom circuits. JiffyTune is a new circuit optimization tool that automates the tuning task. Delay, rise/fall time, area and power targets are accommodated. Each (weighted) target can be either a constraint or an objective function. Minimax optimization is supported. Transistors can be ratioed and similar structures grouped to ensure regular layouts. Bounds on transistor widths are supported. JiffyTune uses LANCELOT, a large-scale nonlinear optimization package with an augmented Lagrangian formulation. Simple bounds are handled explicitly and trust region methods are applied to minimize a composite objective function. In the inner loop of the optimization, the fast circuit simulator SPECS is used to evaluate the circuit. SPECS is unique in its ability to efficiently provide time-domain sensitivities, thereby enabling gradient-based optimization. Both the adjoint and direct methods of sensitivity computation have been implemented in SPECS. To assist the user, interfaces in the Cadence and SLED design systems have been constructed. These interfaces automate the specification of the optimization task, the running of the optimizer and the back-annotation of the results on to the circuit schematic. JiffyTune has been used to tune over 100 circuits for a custom, high-performance microprocessor that makes use of dynamic logic circuits. Circuits with over 250 tunable transistors have been successfully optimized. Automatic circuit tuning has been found to facilitate design re-use. The designers' focus shifts from solving the optimization problem to specifying it correctly and completely. This paper describes the algorithms of JiffyTune, the environment in which it is used and presents a case study of the application of JiffyTune to individual circuits of the microprocessor.