The design and analysis of VLSI circuits
The design and analysis of VLSI circuits
Graph-Based Algorithms for Boolean Function Manipulation
IEEE Transactions on Computers
Verity—a formal verification program for custom CMOS circuits
IBM Journal of Research and Development - Special issue: IBM CMOS technology
A half-micron CMOS logic generation
IBM Journal of Research and Development - Special issue: IBM CMOS technology
Modeling and characterization of long on-chip interconnections for high-performance microprocessors
IBM Journal of Research and Development
Analysis and Design of Analog Integrated Circuits
Analysis and Design of Analog Integrated Circuits
Automation of IC layout with analog constraints
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Efficient linear circuit analysis by Pade approximation via the Lanczos process
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Global harmony: coupled noise analysis for full-chip RC interconnect networks
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Efficient coupled noise estimation for on-chip interconnects
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Optimization techniques for high-performance digital circuits
ICCAD '97 Proceedings of the 1997 IEEE/ACM international conference on Computer-aided design
Design methodology for the S/390 parallel enterprise server G4 microprocessors
IBM Journal of Research and Development - Special issue: IBM S/390 G3 and G4
Timing metrics for physical design of deep submicron technologies
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Analysis, reduction and avoidance of crosstalk on VLSI chips
ISPD '98 Proceedings of the 1998 international symposium on Physical design
Design methodologies for noise in digital integrated circuits
DAC '98 Proceedings of the 35th annual Design Automation Conference
Noise considerations in circuit optimization
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Energy-efficiency in presence of deep submicron noise
Proceedings of the 1998 IEEE/ACM international conference on Computer-aided design
Chip-level verification for parasitic coupling effects in deep-submicron digital designs
DATE '99 Proceedings of the conference on Design, automation and test in Europe
Converting a 64b PowerPC processor from CMOS bulk to SOI technology
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Energy-efficient dynamic circuit design in the presence of crosstalk noise
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Energy-efficient signal processing via algorithmic noise-tolerance
ISLPED '99 Proceedings of the 1999 international symposium on Low power electronics and design
Proceedings of the 37th Annual Design Automation Conference
Domino logic synthesis minimizing crosstalk
Proceedings of the 37th Annual Design Automation Conference
Modeling crosstalk noise for deep submicron verification tools
Proceedings of the conference on Design, automation and test in Europe
Transistor sizing for reliable domino logic design in dual threshold voltage technologies
GLSVLSI '01 Proceedings of the 11th Great Lakes symposium on VLSI
Improved crosstalk modeling for noise constrained interconnect optimization
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
A decoupling method for analysis of coupled RLC interconnects
Proceedings of the 12th ACM Great Lakes symposium on VLSI
Early probabilistic noise estimation for capacitively coupled interconnects
SLIP '02 Proceedings of the 2002 international workshop on System-level interconnect prediction
Soft digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - System Level Design
Estimation of the likelihood of capacitive coupling noise
Proceedings of the 39th annual Design Automation Conference
Efficient switching window computation for cross-talk noise
Proceedings of the 8th ACM/IEEE international workshop on Timing issues in the specification and synthesis of digital systems
A twisted-bundle layout structure for minimizing inductive coupling noise
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Practical considerations in RLCK crosstalk analysis for digital integrated circuits
Proceedings of the 2001 IEEE/ACM international conference on Computer-aided design
Conquering Noise in Deep-Submicron Digital ICs
IEEE Design & Test
Signal integrity management in an SoC physical design flow
Proceedings of the 2003 international symposium on Physical design
Noise propagation and failure criteria for VLSI designs
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Efficient crosstalk noise modeling using aggressor and tree reductions
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Static noise analysis with noise windows
Proceedings of the 40th annual Design Automation Conference
Cross-Coupled Noise Propagation in VLSI Designs
Analog Integrated Circuits and Signal Processing
The Impact of Bit-Line Coupling and Ground Bounce on CMOS SRAM Performance
VLSID '03 Proceedings of the 16th International Conference on VLSI Design
A Model for Crosstalk Noise Evaluation in Deep Submicron Processes
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
CAD Issues for CMOS VLSI Design in SOI
ISQED '01 Proceedings of the 2nd International Symposium on Quality Electronic Design
Coupling Noise Analysis for VLIS and ULSI Circuits
ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power MIMO signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on the 2001 international conference on computer design (ICCD)
Optimal Algorithm for Minimizing the Number of Twists in an On-Chip Bus
Proceedings of the conference on Design, automation and test in Europe - Volume 2
Coding for system-on-chip networks: a unified framework
Proceedings of the 41st annual Design Automation Conference
Static timing analysis using backward signal propagation
Proceedings of the 41st annual Design Automation Conference
Adapative Error Protection for Energy Efficiency
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Reliable low-power digital signal processing via reduced precision redundancy
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
On circuit techniques to improve noise immunity of CMOS dynamic logic
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Noise Library Characterization for Large Capacity Static Noise Analysis Tools
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
A Comprehensive Methodology for Noise Characterization of ASIC Cell Libraries
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Self-timed communication platform for implementing high-performance systems-on-chip
Integration, the VLSI Journal - Special issue: Networks on chip and reconfigurable fabrics
Design and analysis of an NoC architecture from performance, reliability and energy perspective
Proceedings of the 2005 ACM symposium on Architecture for networking and communications systems
Analytical modeling of crosstalk noise waveforms using Weibull function
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
BBE: hierarchical computation of 3-D interconnect capacitance with BEM block extraction
ASP-DAC '03 Proceedings of the 2003 Asia and South Pacific Design Automation Conference
Performance driven reliable link design for networks on chips
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Noise margin analysis for dynamic logic circuits
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Accurate delay computation for noisy waveform shapes
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Energy-efficient soft error-tolerant digital signal processing
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Crosstalk minimization in logic synthesis for PLAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
On-Chip Communication Architectures: System on Chip Interconnect
On-Chip Communication Architectures: System on Chip Interconnect
Top-k aggressors sets in delay noise analysis
Proceedings of the 44th annual Design Automation Conference
Modeling Power Supply Noise in Delay Testing
IEEE Design & Test
Fault-aware communication mapping for NoCs with guaranteed latency
International Journal of Parallel Programming
A robust finite-point based gate model considering process variations
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Victim alignment in crosstalk aware timing analysis
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Performance-Optimized Design for Parametric Reliability
Journal of Electronic Testing: Theory and Applications
Noise separation in analog integrated circuits using independent component analysis technique
Integrated Computer-Aided Engineering
IBM POWER6 microprocessor physical design and design methodology
IBM Journal of Research and Development
Compound noise separation in digital circuits using blind source separation
Microelectronics Journal
Controllability of Static CMOS Circuits for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation
Error-resilient motion estimation architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Deflecting crosstalk by routing reconsideration through refined signal correlation estimation
Proceedings of the 19th ACM Great Lakes symposium on VLSI
A study on impact of aggressor de-rating in the context of multiple crosstalk effects in circuits
Proceedings of the 19th ACM Great Lakes symposium on VLSI
Chip integration methodology for the IBM S/390 G5 and G6 custom microprocessors
IBM Journal of Research and Development
IBM eServer z900 high-frequency microprocessor technology, circuits, and design methodology
IBM Journal of Research and Development
Victim alignment in crosstalk-aware timing analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
An analytical approach to dynamic crosstalk in coupled interconnects
Microelectronics Journal
Interconnect performance corners considering crosstalk noise
ICCD'09 Proceedings of the 2009 IEEE international conference on Computer design
Error resilience of intra-die and inter-die communication with 3D Spidergon STNoC
Proceedings of the Conference on Design, Automation and Test in Europe
Stochastic networked computation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Realistic scalability of noise in dynamic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Coding for system-on-chip networks: a unified framework
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Crosstalk noise reduction in synthesized digital logic circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Full-chip TSV-to-TSV coupling analysis and optimization in 3D IC
Proceedings of the 48th Design Automation Conference
Integration, the VLSI Journal
Journal of Computer and System Sciences
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper defines noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is defined, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with on-chip interconnect are also considered. This paper concludes with a discussion of the device, ciruit, layout, and logic design issues associated with noise.