Noise in deep submicron digital design
Proceedings of the 1996 IEEE/ACM international conference on Computer-aided design
Closed-loop adaptive voltage scaling controller for standard-cell ASICs
Proceedings of the 2002 international symposium on Low power electronics and design
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
On-chip delay measurement for silicon debug
Proceedings of the 14th ACM Great Lakes symposium on VLSI
IEEE Micro
Redundancy & It's Not Just for Defects Anymore
MTDT '04 Proceedings of the Records of the 2004 International Workshop on Memory Technology, Design and Testing
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
A Scheme for On-Chip Timing Characterization
VTS '06 Proceedings of the 24th IEEE VLSI Test Symposium
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Process variations have a significant impact on behavior of integrated circuits (ICs) designed in deep sub-micron (DSM) technologies, and it has been estimated that in some cases up to a generation of performance can be lost due to process variations (Bowman et al., IEEE J Solid State Circuits 37:183---190, 2002), making it a significant problem for design and manufacture of DSM ICs. Adaptive design techniques are fast evolving as a potential solution to this problem. Such techniques facilitate reconfiguration of an IC to enable its operation across process corners, thus ensuring parametric reliability in such ICs, and also improving manufacturing yield. In this paper, adaptive design techniques with a focus on timing of ICs, i.e., performance-optimized adaptive design, are explored. The focus of such performance-optimized adaptive design techniques is to ensure that adaptation does not cause an IC to violate timing specifications, thus giving priority to performance, which remains one of the most important parameters of an IC.