Performance-Optimized Design for Parametric Reliability
Journal of Electronic Testing: Theory and Applications
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As we introduce this yearýs Hot Chips theme issue, the frequency slowdown trend that is upon us as a result of the CMOS technology outlook has to be the single major point that stands out. It is not just the per-chip power dissipation envelope that is forcing this trend, although that factor alone is perhaps the major deterrent to frequency escalation at prior (historical) rates.