Performance-Optimized Design for Parametric Reliability
Journal of Electronic Testing: Theory and Applications
Path-RO: a novel on-chip critical path delay measurement under process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
A delay measurement method using a shrinking clock signal
Proceedings of the 20th symposium on Great lakes symposium on VLSI
On-Chip Delay Measurement Based Response Analysis for Timing Characterization
Journal of Electronic Testing: Theory and Applications
Provably complete hardware trojan detection using test point insertion
Proceedings of the International Conference on Computer-Aided Design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-precision on-chip path delay measurement architecture
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Path delay fault simulation performance on multi-cycle delay paths common in industrial designs is discussed using paths from a large block in a microprocessor and a functional test vector suite. We profile fault simulation performance using a novel ...