On-Chip Delay Measurement Based Response Analysis for Timing Characterization

Authors:
Ramyanshu Datta;Antony Sebastine;Ashwin Raghunathan;Gary Carpenter;Kevin Nowka;Jacob A. Abraham
Affiliations:
Computer Engineering Research Center, The University of Texas at Austin, Austin, USA 78712-0323;Computer Engineering Research Center, The University of Texas at Austin, Austin, USA 78712-0323;Computer Engineering Research Center, The University of Texas at Austin, Austin, USA 78712-0323;IBM Research, Austin, USA 78758;IBM Research, Austin, USA 78758;Computer Engineering Research Center, The University of Texas at Austin, Austin, USA 78712-0323
Venue:
Journal of Electronic Testing: Theory and Applications
Year:
2010

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Abstract

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.